//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module ETH10G_TOP(

   input                   ETH10G_RESET,

   input                   ETH10G_RFCLK_0P,
   input                   ETH10G_RFCLK_0N,

   input                   ETH10G_AFE_RXD_0P,
   input                   ETH10G_AFE_RXD_0N,
   input                   ETH10G_AFE_RXD_1P,
   input                   ETH10G_AFE_RXD_1N,
   input                   ETH10G_AFE_RXD_2P,
   input                   ETH10G_AFE_RXD_2N,
   input                   ETH10G_AFE_RXD_3P,
   input                   ETH10G_AFE_RXD_3N,

   input                   ETH10G_AFE_TXD_0P,
   input                   ETH10G_AFE_TXD_0N,
   input                   ETH10G_AFE_TXD_1P,
   input                   ETH10G_AFE_TXD_1N,
   input                   ETH10G_AFE_TXD_2P,
   input                   ETH10G_AFE_TXD_2N,
   input                   ETH10G_AFE_TXD_3P,
   input                   ETH10G_AFE_TXD_3N,

   input                   ETH10G_IN_SIGDECT
   );


configuration_vector


ETH10G_PCS_block              ETH10G_PCS_0(
   .refclk_n                  ( ETH10G_RFCLK_0P ),
   .refclk_p                  ( ETH10G_RFCLK_0N ),
   .clk156                    (  ),
   .txclk322                  (  ),
   .rxclk322                  (  ),
   .dclk                      (  ),
   .areset                    ( ETH10G_RESET ),
   .reset                     ( ETH10G_RESET ),
   .rxreset322                ( ETH10G_RESET ),
   .txreset322                ( ETH10G_RESET ),
   .dclk_reset                ( ETH10G_RESET ),
   .xgmii_txd                 (  ),
   .xgmii_txc                 (  ),
   .xgmii_rxd                 (  ),
   .xgmii_rxc                 (  ),
   .txp                       ( ETH10G_AFE_TXD_0P ),
   .txn                       ( ETH10G_AFE_TXD_0N ),
   .rxp                       ( ETH10G_AFE_RXD_0P ),
   .rxn                       ( ETH10G_AFE_RXD_0N ),
   .configuration_vector      ( ),
   .status_vector             ( ),
   .core_status               ( ),
   .tx_resetdone              ( ),
   .rx_resetdone              ( ),
   .signal_detect             ( ETH10G_IN_SIGDECT ),
   .tx_fault                  (  ),
   .tx_disable                (  )
   );

ETH10G_PCS_block              ETH10G_PCS_1(
   .refclk_n                  ( ETH10G_RFCLK_0P ),
   .refclk_p                  ( ETH10G_RFCLK_0N ),
   .clk156                    (  ),
   .txclk322                  (  ),
   .rxclk322                  (  ),
   .dclk                      (  ),
   .areset                    ( ETH10G_RESET ),
   .reset                     ( ETH10G_RESET ),
   .rxreset322                ( ETH10G_RESET ),
   .txreset322                ( ETH10G_RESET ),
   .dclk_reset                ( ETH10G_RESET ),
   .xgmii_txd                 (  ),
   .xgmii_txc                 (  ),
   .xgmii_rxd                 (  ),
   .xgmii_rxc                 (  ),
   .txp                       ( ETH10G_AFE_TXD_0P ),
   .txn                       ( ETH10G_AFE_TXD_0N ),
   .rxp                       ( ETH10G_AFE_RXD_0P ),
   .rxn                       ( ETH10G_AFE_RXD_0N ),
   .configuration_vector      ( ),
   .status_vector             ( ),
   .core_status               ( ),
   .tx_resetdone              ( ),
   .rx_resetdone              ( ),
   .signal_detect             ( ETH10G_IN_SIGDECT ),
   .tx_fault                  (  ),
   .tx_disable                (  )
   );

ETH10G_PCS_block              ETH10G_PCS_2(
   .refclk_n                  ( ETH10G_RFCLK_0P ),
   .refclk_p                  ( ETH10G_RFCLK_0N ),
   .clk156                    (  ),
   .txclk322                  (  ),
   .rxclk322                  (  ),
   .dclk                      (  ),
   .areset                    ( ETH10G_RESET ),
   .reset                     ( ETH10G_RESET ),
   .rxreset322                ( ETH10G_RESET ),
   .txreset322                ( ETH10G_RESET ),
   .dclk_reset                ( ETH10G_RESET ),
   .xgmii_txd                 (  ),
   .xgmii_txc                 (  ),
   .xgmii_rxd                 (  ),
   .xgmii_rxc                 (  ),
   .txp                       ( ETH10G_AFE_TXD_0P ),
   .txn                       ( ETH10G_AFE_TXD_0N ),
   .rxp                       ( ETH10G_AFE_RXD_0P ),
   .rxn                       ( ETH10G_AFE_RXD_0N ),
   .configuration_vector      ( ),
   .status_vector             ( ),
   .core_status               ( ),
   .tx_resetdone              ( ),
   .rx_resetdone              ( ),
   .signal_detect             ( ETH10G_IN_SIGDECT ),
   .tx_fault                  (  ),
   .tx_disable                (  )
   );

ETH10G_PCS_block              ETH10G_PCS_3(
   .refclk_n                  ( ETH10G_RFCLK_0P ),
   .refclk_p                  ( ETH10G_RFCLK_0N ),
   .clk156                    (  ),
   .txclk322                  (  ),
   .rxclk322                  (  ),
   .dclk                      (  ),
   .areset                    ( ETH10G_RESET ),
   .reset                     ( ETH10G_RESET ),
   .rxreset322                ( ETH10G_RESET ),
   .txreset322                ( ETH10G_RESET ),
   .dclk_reset                ( ETH10G_RESET ),
   .xgmii_txd                 (  ),
   .xgmii_txc                 (  ),
   .xgmii_rxd                 (  ),
   .xgmii_rxc                 (  ),
   .txp                       ( ETH10G_AFE_TXD_0P ),
   .txn                       ( ETH10G_AFE_TXD_0N ),
   .rxp                       ( ETH10G_AFE_RXD_0P ),
   .rxn                       ( ETH10G_AFE_RXD_0N ),
   .configuration_vector      ( ),
   .status_vector             ( ),
   .core_status               ( ),
   .tx_resetdone              ( ),
   .rx_resetdone              ( ),
   .signal_detect             ( ETH10G_IN_SIGDECT ),
   .tx_fault                  (  ),
   .tx_disable                (  )
   );


endmodule


